// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:07 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  gen_clk_gate.v
//
//  Generic clock gate module
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: kainie $
//    $File: //dwh/up16/main/dev/pma/dig/rtl/gen_clk_gate.v $
//    $DateTime: 2013/09/17 12:10:56 $
//    $Revision: #4 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_ani_techcell_lib.v"

module dwc_e12mp_phy_x4_ns_gen_clk_gate (
output wire en_clk,
input  wire clk,
input  wire rst,
input  wire en,
input  wire scan_mode_i,
input  wire scan_shift_cg_i,
input  wire scan_set_rst_i
);

// The parameter selects whether enable is active or inactive during reset
//
parameter RST_ON = 1'b0; 

// Latch enable to ensure it is stable while clock is high.  May
// need hand-instantiated latch here.  Assuming that reset is
// synchronous with the clock and that input clock is toggling
// (otherwise it wouldn't really be all that helpful to override
// the enable during reset).
//
// ASSERT: add assertion to validate assumption
//

// Need to instantiate a gen_mux to force a mux structure.
// Optimized gate-structed muxes cause TSV-118 DFT violations. 
wire my_en;
dwc_e12mp_phy_x4_ns_gen_mux my_en_rst_mux (
  .out (my_en),
  .sel (rst & ~scan_mode_i),
  .d0  (en),
  .d1  (RST_ON)
);

// Gated clock - latch and AND gate hand-instantiated as stdcell
//
// %%SYNTH:
//   set_size_only -all_instances [get_cells $inst/hand_clk_gate]
//
`ifdef ANI_SYNTH_MODE
   dwc_e12mp_phy_x4_ns_ani_clk_gate hand_clk_gate (
     .ECK (en_clk),
     .CK  (clk),
     .E   (my_en),
     .SE  (scan_shift_cg_i)
   );

  // ATPG cover-point on functional clk enable
  reg  atpg_cov;
  always @(posedge clk or posedge scan_set_rst_i) begin
    if (scan_set_rst_i)
      atpg_cov <= 1'b0;
    else
      atpg_cov <= my_en; 
  end
`else    
  reg en_f;
  always @(clk or scan_shift_cg_i or my_en)
    if (!clk)
      en_f <= scan_shift_cg_i || my_en;

   assign en_clk = en_f & clk;

  // ATPG cover-point on functional clk enable
  reg atpg_cov;
  always @(posedge clk or posedge scan_set_rst_i) begin
    if (scan_set_rst_i)
      atpg_cov <= 1'b0;
    else
      atpg_cov <= my_en; 
  end

`endif

endmodule
